Low-power Synthesis of Combinational Cmos Circuits

An approach to logic synthesis using CMOS element library is suggested, it allows to minimize the area and the average value of power consumption of microcircuit implemented on CMOS VLSI chip. The case of synthesis of combinational CMOS networks is considered when, for the purposes of energy estimation during the synthesis process, the static method based on probabilistic properties of input signals is used. The synthesis is comprised of the technology independent phase where logic minimization and decomposition are performed on the Boolean functions equations and the technology dependent phase where mapping to a physical cell library is performed.